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TSTS1 TSTS c (S, I, O) = {(S, T c (I), T c (O), , s0) STS(S, T c (I), T c (O)) | : s t #o = 1 i/o i /o : s t, i : t : : s t } TSTS c (S, I, O) is the set of all, possibly underspeci ed STSs that resemble timed object behavior. A TSTS has a complete transition relation. The restriction #o = 1 in TSTS is not a real one, as by de nition o (T (O)) , which can be regarded as equivalent to o T (O). Instead, we could also use a attening operator on o. The simpli ed representation of the timed transition function , which will now be used, is thus : (S T c (I)) P(S T c (O)) where T c (I) denotes the set of channel time slices for the channels in I. The second restriction models the fact that the state transition function describes the behavior of a Moore machine [5]. The output o therefore depends only on the start state s, not on the input x, as for all other inputs x the same output y is happening, too. One way to interpret this rule is that the granularity of time is ne enough to trace state changes in such a detailed way that the reaction to an input is always delayed by at least one time unit (one state transition step). As an immediate consequence, feedback cycles include a time step and thus preserve causality. Another consequence is that the output of a transition is independent of the input of this transition and intermediate storage for either the input before being processed or the resulting output in the state space is therefore inevitable.

iv If bit 1 of CWR register is at logic 0 , portAenable is driven to logic 1 If bit 1 of CWR register is at logic 1 , portAenable is driven to logic 0 b Bits 6 and 5 of CWR register are checked for their value Assume CWR[6:5] is at logic 01 (mode 1 operation) i If bit 2 of CWR register is at logic 0 , portBenable is driven to logic 1 If bit 2 of CWR register is at logic 1 , portBenable is driven to logic 0 ii If bit 1 of CWR register is at logic 0 , portAenable is driven to logic 1 If bit 1 of CWR register is at logic 1 , portAenable is driven to logic 0 iii If CWR[2:1] register is at logic 00 (portA and portB function as strobed output), portCenable is driven to logic 10001011 .

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2 de nes source(t) = {U} and target(t) = {X, Z} The scope of t is the closest common ancestor of {U, X, Z}, which is S, thus entered(t) = {V , W , X, Y , Z} and exited(t) = {U, T } We also have that source(u) = {U} = target(u) The scope of u is the closest common ancestor of {U}, which is T , thus entered(u) = {U} = exited(u) Given a state set ss, the implicit children are those children of AND states of ss that are not in ss.

The Detail section is in fairly good shape. Make sure the Description control is slightly indented from the Category expression in the Group Header. A label should be created, as shown in Figure 9.37, identifying the values in the Cost and Retail Price controls. A line is also good to add to this Detail section to separate one record from another. This is often done when records occupy varying space within a group. Some records are shorter than others, and the separation between records might not be obvious to users. Because you don t want two lines at the bottom of each page (you add a line to the Page Footer next), you put this line at the top of the Detail section:

If a chart is in ss, it is also in all its implicit children: imp(ss) = children[ss AND] ss The completion of a transition t is the set of all transitions that are taken when t is taken: It adds all default transitions of XOR targets of t and all default transitions of implicit targets of t comp(t) = {t} s (target(t) XOR) imp(entered(t)) comp(default(s)).

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